The invention generally relates to making MOSFETs with vertical gates of strained Si, and more particularly relates to making single gate and double gate MOSFETS and finFETS with vertical gates of strained Si.
As semiconductor devices shrink, traditional device fabrication techniques have approached practical limits in size scaling. For example, as channel lengths shrink below about 50 nm, devices start to exhibit short channel effects including threshold voltage rolling off for shortened channel lengths. Unwanted short channel effects may be reduced by higher doping concentrations, which lead to the unwanted effects of carrier mobility degradation, increased parasitic junction capacitance, and increased sub-threshold swing if doping concentrations become too high.
One method to minimize short channel and reverse short channel effects includes striking an optimum doping profile by well controlled implantation and annealing. However, carefully controlling implantation and annealing adds costs to the fabrication process, and are ultimately limited in effectiveness as channel lengths are further reduced. Scaling limits imposed due to the limitation of gate oxide thickness and source/drain junction depth may also arise to impair function of the smaller devices.
Another method to achieve further reduced scale includes difficult to manufacture profiles for the channel. Such profiles include double gate, triple gate, quadruple gate, omega-gate, pi-gate, and finFET MOSFET designs. Some of these designs are plagued with design problems such as gate alignment errors leading to increased parasitic capacitance.
Another possible way to avoid some scaling problems is to improve device performance by improving material performance. For example, strained Si produces higher mobility of carriers resulting in faster and/or lower power consumption devices. Due to changes in strained Si crystalline structure (i.e. its symmetry and lattice constant are different due to its strain state), a strained Si film has electronic properties that are superior to those of bulk Si. Specifically, the strained Si could have greater electron and hole mobilities, which translate into greater drive current capabilities for n-type and p-type transistors, respectively. Accordingly, devices incorporating strained Si may have improved performance without necessarily reducing device size. However, where the strained Si does allow for further scaling, performance improvement will be further improved.
It should be noted, however, an important criteria in enabling high-performance devices by utilizing strained Si is the fabrication of a low-defect-density strained Si film. In particular, reducing the number of dislocations in the strained Si film is especially important in order to reduce leakage and improve carrier mobility.
Growing a Si layer on a substrate having lattice parameters different from the Si, generates the strained Si film. Accordingly, the number of defects in the strained Si film may be proportional to the number of defects in the underlying substrate on which the film is grown. An increase in the number of dislocations in the Si channel can increase the leakage current in the device while in the “off” stage. When formed improperly, the strained Si film can contain a high number of defects and the subsequent strained Si film will then exhibit poor performance characteristics, and any benefits of using a strained Si film will be substantially negated.
Accordingly, producing strained Si films having minimal defects such as dislocations is desirable for further reduction in semiconductor device size and power requirements. Thin strained Si films having few defects may lead to improved semiconductor device performance